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Steps for Writing a Speed-of-Light GEMM kernel: Part 1

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Luke D. Huang

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Steps for Writing a Speed-of-Light GEMM kernel: Part 1 is Luke D. Huang's August 2026 blog article opening a CuTeDSL series on BF16 matrix multiplication for NVIDIA B200 Blackwell GPUs. Huang documents nine planned kernel iterations that move from a correct baseline toward roughly ninety-nine percent of cuBLAS throughput on several problem sizes.

Part 1 introduces the GPU programming model for GEMM, builds a naive per-thread matmul baseline near four TFLOP/s, then adds tensor-core MMA via tcgen05, TMA loads, TMEM accumulators, and shared-memory tiling to reach about 155 TFLOP/s. A third kernel attacks shared-memory bank conflicts through swizzled layouts alone, lifting performance to about 285 TFLOP/s before later posts cover pipelines, warp specialization, and persistent scheduling.

The series targets advanced CUDA programmers learning CuTeDSL's tile abstractions and Blackwell-specific features. Familiarity with warp-level execution, shared memory, and basic linear algebra notation helps, because each section states the bottleneck, shows the code change, and reports measured timings.

Huang's matmul walkthrough is cited in GPU.