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Blackwell: Nvidia’s Massive GPU

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Chester Lam

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This is a June 2025 Chips and Cheese architecture deep dive by Chester Lam measuring Nvidia's largest consumer Blackwell GPU, focused on GB202 configurations such as the RTX PRO 6000 Blackwell versus AMD RDNA4 parts like the RX 9070.

It covers die scale, SM and GPC work distribution, removal of subchannel switches for mixed graphics and compute queues, SM frontend instruction caches, execution unit layout, uniform datapath FP ops, ray triangle rate claims, L1 and shared memory ports, atomics, L2 and VRAM latency or bandwidth, and FluidX3D compute examples. Comparisons repeatedly contrast Nvidia's high SM count with AMD's stronger per-WGP building blocks.

It is for advanced GPU architects, driver engineers, and performance-minded graphics programmers who read microbenchmarks. Comfort with SM or WGP terminology and cache hierarchies is assumed.

Access is a free long-form HTML article on chipsandcheese.com with charts, acknowledgements, and reference links; comments appear below the post.

It is useful when reasoning about Blackwell client GPU scale, memory subsystem tradeoffs, and where occupancy or cache behavior may limit large dispatches.