Memory-Efficient BVHs with Merged Nodes for Hardware Ray Tracing
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Jacob Haydel, Andrew Kensler, Erik Brunvand, Cem Yuksel
Visit resource ↗Description
Memory-Efficient BVHs with Merged Nodes for Hardware Ray Tracing presents a block-based wide BVH layout that merges internal and leaf nodes to cut pointer overhead on GPUs.
The Utah Graphics Lab HPG 2026 work reformulates SAH construction with a memory-centric cost model so builders favor layouts that reduce bandwidth per ray rather than only traditional surface-area heuristics.
Reported results include smaller BVHs, lower memory traffic during traversal, and faster path-traced frame times versus a strong wide-BVH baseline on hardware ray tracing paths.
The audience is advanced rendering engineers implementing or tuning GPU ray tracing kernels and acceleration structures.
HPG and Utah Lab BVH notes are frequently bookmarked by engineers optimizing RT pipelines in research renderers and game engines.
Link last verified accessible on 2026-09-28.
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